1. Field of the Invention
The present invention relates to technology for non-volatile storage.
2. Description of the Related Art
Semiconductor memory has become more popular for use in various electronic devices. For example, non-volatile semiconductor memory is used in personal navigation devices, cellular telephones, digital cameras, personal digital assistants, mobile computing devices, non-mobile computing devices and other devices. Electrical Erasable Programmable Read Only Memory (EEPROM) and flash memory are among the most popular non-volatile semiconductor memories.
Both EEPROM and flash memory utilize a floating gate that is positioned above and insulated from a channel region in a semiconductor substrate. The floating gate and channel regions are positioned between the source and drain regions. A control gate is provided over and insulated from the floating gate. The threshold voltage of the transistor is controlled by the amount of charge that is retained on the floating gate. That is, the minimum amount of voltage that must be applied to the control gate before the transistor is turned on to permit conduction between its source and drain is controlled by the level of charge on the floating gate.
Some EEPROMs or flash memory devices have a configuration referred to as a NAND configuration in which memory cells are grouped as NAND strings with each NAND string associated with a bit line. When programming an EEPROM or flash memory device, such as a NAND flash memory device, typically a program voltage is applied to the control gate and the bit line is grounded. Electrons from the channel are injected into the floating gate. When electrons accumulate in the floating gate, the floating gate becomes negatively charged and the threshold voltage of the memory cell is raised so that the memory cell is in a programmed state. More information about programming can be found in U.S. Pat. No. 6,859,397, titled “Source Side Self Boosting Technique for Non-Volatile Memory;” U.S. Pat. No. 6,917,542, titled “Detecting Over Programmed Memory;” and U.S. Pat. No. 6,888,758, titled “Programming Non-Volatile Memory,” all three cited patents are incorporated herein by reference in their entirety.
In many cases, the program voltage is applied to the control gate as a series of pulses (referred to as programming pulses), with the magnitude of the pulses increasing with each pulse. Between programming pulses, a set of one or more verify operations are performed to determine whether the memory cell(s) being programmed have reached their target level. If a memory cell has reached its target level, programming stops for that memory cell. If a memory cell has not reached its target level, programming will continue for that memory cell.
Shifts in the apparent charge stored on a floating gate can occur because of the coupling of an electric field based on the charge stored in adjacent floating gates. This phenomenon is described in U.S. Pat. No. 5,867,429, which is incorporated herein by reference in its entirety. The problem occurs most pronouncedly between sets of adjacent memory cells that have been programmed at different times. For example, a first memory cell is programmed to add a level of charge to its floating gate that corresponds to one set of data. Subsequently, one or more adjacent memory cells are programmed to add a level of charge to their floating gates that correspond to a second set of data. After the one or more of the adjacent memory cells are programmed, the charge level read from the first memory cell appears to be different than programmed because of the effect of the charge on the adjacent memory cells being coupled to the first memory cell. The coupling from adjacent memory cells can shift the apparent charge level being read a sufficient amount to lead to an erroneous reading of the data stored. Note that the floating gate coupling problems can be due to coupling between adjacent floating gates (floating gate-to-floating gate coupling) and from a channel of one memory cell to the floating gate of an adjacent memory cell (channel-to-floating gate).
The effect of the floating gate coupling is of greater concern for multi-state devices because multi-state devices typically have smaller threshold voltage margins between states than that of binary devices, in addition to storing greater amounts of charge. Additionally, the difference in charge stored between the lowest state and the highest state of a multi-state device is likely to be greater than the difference in charge stored between the erased and programmed states of a binary memory device. The magnitude of the voltage coupled between adjacent floating gates is based on the magnitude of charge stored on the adjacent floating gates.
In some implementations, each NAND string is connected to a number of data word lines and one or more dummy word lines. Each memory cell on a NAND string is connected to one of the word lines. A given word line is connected to numerous NAND strings. For example, a NAND string may have 64 memory cells that store user data (each of which is connected to a separate word line) and one or more dummy memory cells that do not store user data (connected to dummy word lines). Dummy memory cells that are connected to the dummy word lines are not used for data storage. In a memory array that uses dummy word lines, some of the data memory cells have another data memory cell on each side. However, a memory cell at the end of the NAND string has a data memory cell on one side and a dummy memory cell on the other side. This can lead to differences in the amount of floating gate coupling that is experienced by memory cells on the last word line.